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general description the max5883 is an advanced, 12-bit, 200msps digital- to-analog converter (dac) designed to meet the demanding performance requirements of signal synthe- sis applications found in wireless base stations and other communications applications. operating from a single 3.3v supply, this dac offers exceptional dynamic performance such as 77dbc spurious-free dynamic range (sfdr) at f out = 10mhz. the dac supports update rates of 200msps at a power dissipation of less than 200mw. the max5883 utilizes a current-steering architecture, which supports a full-scale output current range of 2ma to 20ma, and allows a differential output voltage swing between 0.1v p-p and 1v p-p . the max5883 features an integrated 1.2v bandgap reference and control amplifier to ensure high accuracy and low noise performance. additionally, a separate reference input pin enables the user to apply an exter- nal reference source for optimum flexibility and to improve gain accuracy. the digital and clock inputs of the max5883 are designed for cmos-compatible voltage levels. the max5883 is available in a 48-pin qfn package with an exposed paddle (ep) and is specified for the extended industrial temperature range (-40? to +85?). refer to the max5884 and max5885 data sheets for pin-compatible 14- and 16-bit versions of the max5883. for lvds high-speed versions, refer to the max5886, max5887, and max5888 data sheets. applications base stations: single/multicarrier umts, cdma communications: lmds, mmds, point-to-point microwave digital signal synthesis automated test equipment (ate) instrumentation features 200msps output update rate single 3.3v supply operation excellent sfdr and imd performance sfdr = 77dbc at f out = 10mhz (to nyquist) imd = -86dbc at f out = 10mhz aclr = 71db at f out = 30.72mhz 2ma to 20ma full-scale output current cmos-compatible digital and clock inputs on-chip 1.2v bandgap reference low power dissipation 48-pin qfn-ep package max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs ________________________________________________________________ maxim integrated products 1 ordering information 19-2824; rev 1; 12/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max5883egm -40 c to +85 c 48 qfn-ep* b8 b9 b11 dgnd n.c. n.c. n.c. n.c. n.c. dv dd sel0 b10 xor vclk clkgnd clkp clkn clkgnd vclk pd av dd agnd n.c. n.c. 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 agnd ioutn ioutp av dd agnd av dd agnd n.c. dacref fsadj refio n.c. b0 b1 b2 dv dd dgnd b3 b4 b5 b7 b6 n.c. qfn max5883 agnd top view 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 pin configuration * ep = exposed paddle.
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = dv dd = vclk = 3.3v, agnd = dgnd = clkgnd = 0v, external reference, v refio = 1.25v, r l = 50 ? , i out = 20ma, f clk = 200msps, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd , dv dd , vclk to agnd................................-0.3v to +3.9v av dd , dv dd , vclk to dgnd ...............................-0.3v to +3.9v av dd , dv dd , vclk to clkgnd ...........................-0.3v to +3.9v agnd, clkgnd to dgnd....................................-0.3v to +0.3v dacref, refio, fsadj to agnd.............-0.3v to av dd + 0.3v ioutp, ioutn to agnd................................-1v to av dd + 0.3v clkp, clkn to clkgnd...........................-0.3v to vclk + 0.3v b0 b11, sel0, pd, xor to dgnd.............-0.3v to dv dd + 0.3v continuous power dissipation (t a = +70 c) 48-pin qfn (derate 27mw/ c above +70 c)............2162.2mw thermal resistance ( ja ) ..............................................+37 c/w operating temperature range ..........................-40 c to +85 c junction temperature .....................................................+150 c storage temperature range ............................-60 c to +150 c lead temperature (soldering, 10s) ................................+300 c parameter symbol conditions min typ max units static performance resolution 12 bits integral nonlinearity inl measured differentially 0.3 lsb differential nonlinearity dnl measured differentially 0.2 lsb offset error os -0.025 0.003 +0.025 %fs offset drift 50 ppm/ c full-scale gain error ge fs external reference, t a +25 c -3.5 +1.3 %fs internal reference 100 gain drift external reference 50 ppm/ c full-scale output current i out (note 1) 2 20 ma min output voltage single ended -0.5 v max output voltage single ended 1.1 v output resistance r out 1m ? output capacitance c out 5pf dynamic performance output update rate f clk 1 200 msps f clk = 100mhz f out = 16mhz, -12db fs -150 noise spectral density f clk = 200mhz f out = 80mhz, -12db fs -148 db fs/ hz f out = 1mhz, 0db fs 87 f out = 1mhz, -6db fs 81 spurious-free dynamic range to nyquist sfdr f clk = 100mhz f out = 1mhz, -12db fs 80 dbc
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = vclk = 3.3v, agnd = dgnd = clkgnd = 0v, external reference, v refio = 1.25v, r l = 50 ? , i out = 20ma, f clk = 200msps, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units f out = 10mhz, -12db 77 f clk = 100mhz f out = 30mhz, -12db 73 f out = 10mhz, -12db 70 f out > 16mhz, -12db fs, t a = +25 c 68 74 f out = 30mhz, -12db 66 spurious-free dynamic range to nyquist sfdr f clk = 200mhz f out = 50mhz, -12db 68 dbc f out1 = 9mhz, -6db f clk = 100mhz f out2 = 10mhz, -6db -86 f out1 = 29mhz, -6db two-tone imd ttimd f clk = 200mhz f out2 = 30mhz, -6db -74 dbc four-tone imd, 1mhz frequency spacing ftimd f clk = 150mhz f out = 32mhz, -12db fs -82 dbc adjacent channel leakage power ratio, 4.1mhz bandwidth, w-cdma model aclr f clk = 184.32mhz f out = 30.72mhz 71 db output bandwidth bw -1db (note 2) 450 mhz reference internal reference voltage range v refio 1.1 1.22 1.34 v reference input compliance range v refiocr 0.125 1.25 v reference input resistance r refio 10 k ? reference voltage drift tco ref 50 ppm/ c analog output timing output fall time t fall 90% to 10% (note 3) 375 ps output rise time t rise 10% to 90% (note 3) 375 ps output voltage settling time t settle output settles to 0.025% fs (note 3) 11 ns output propagation delay t pd (note 3) 1.8 ns glitch energy 1 pv-s i out = 2ma 30 output noise n out i out = 20ma 30 pa/ hz timing characteristics data to clock setup time t setup referenced to rising edge of clock (note 4) 0.4 ns data to clock hold time t hold referenced to rising edge of clock (note 4) 1.25 ns
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs 4 _______________________________________________________________________________________ note 1: nominal full-scale current i out = 32 ? i ref . note 2: this parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the max5883. note 3: parameter measured single ended into a 50 ? termination resistor. note 4: parameter guaranteed by design. note 5: parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltage. electrical characteristics (continued) (av dd = dv dd = vclk = 3.3v, agnd = dgnd = clkgnd = 0v, external reference, v refio = 1.25v, r l = 50 ? , i out = 20ma, f clk = 200msps, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units data latency 3.5 clock cycles minimum clock pulse width high t ch clkp, clkn 1.5 ns minimum clock pulse width low t cl clkp, clkn 1.5 ns cmos logic inputs (b0?11, pd, sel0, xor) input logic high v ih 0.7 x dv dd v input logic low v il 0.3 x dv dd v input leakage current i in -15 +15 a input capacitance c in 5pf clock inputs (clkp, clkn) sine wave 1.5 differential input voltage swing v clk square wave 0.5 v p-p differential input slew rate sr clk (note 5) >100 v/s common-mode voltage range v com 1.5 20% v input resistance r clk 5k ? input capacitance c clk 5pf power supplies analog supply voltage range av dd 3.135 3.3 3.465 v digital supply voltage range dv dd 3.135 3.3 3.465 v clock supply voltage range v clk 3.135 3.3 3.465 v f clk = 100msps, f out = 1mhz 27 analog supply current i avdd power-down 0.3 ma f clk = 100msps, f out = 1mhz 7.5 ma digital supply current i dvdd power-down 10 a f clk = 100msps, f out = 1mhz 5.5 ma clock supply current i vclk power-down 10 a f clk = 100msps, f out = 1mhz 132 power dissipation p diss power-down 1 mw power-supply rejection ratio psrr av dd = vclk = dv dd = 3.3v 5% (note 5) -0.1 +0.1 %fs/v
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs _______________________________________________________________________________________ 5 typical operating characteristics (av dd = dv dd = vclk = 3.3v, external reference, v refio = 1.25v, r l = 50 ? , i out = 20ma, t a = +25 c, unless otherwise noted.) spurious-free dynamic range vs. output frequency (f clk = 50mhz) max5883 toc01 f out (mhz) sfdr (dbc) 20 15 10 5 10 20 30 40 50 60 70 80 90 100 0 025 -6db fs -12db fs 0db fs spurious-free dynamic range vs. output frequency (f clk = 100mhz) max5883 toc02 f out (mhz) sfdr (dbc) 40 30 20 10 10 20 30 40 50 60 70 80 90 100 0 050 -6db fs -12db fs 0db fs spurious-free dynamic range vs. output frequency (f clk = 150mhz) max5883 toc03 f out (mhz) sfdr (dbc) 60 45 30 15 10 20 30 40 50 60 70 80 90 100 0 075 -6db fs -12db fs 0db fs 90 80 60 70 20 30 40 50 10 0100 spurious-free dynamic range vs. output frequency (f clk = 200mhz) max5883 toc04 f out (mhz) sfdr (dbc) 10 20 30 40 50 60 70 80 90 100 0 -6db fs -12db fs 0db fs 2-tone imd vs. output frequency (1mhz carrier spacing, f clk = 100mhz) max5883 toc05 f out (mhz) 2-tone imd (dbc) 40 30 20 10 -50 -60 -70 -80 -90 -100 -40 050 -6db fs -12db fs 2-tone intermodulation distortion (f clk = 100mhz) max5883 toc06 f out (mhz) output power (dbm) 35 34 32 33 26 27 28 29 30 31 25 -90 -80 -70 -60 -50 -40 -30 f t1 f t2 -20 -10 0 -100 24 36 2 x f t1 - f t2 2 x f t2 - f t1 f t1 = 28.9429mhz f t2 = 29.8706mhz a out = -6db fs bw = 12mhz 4-tone power ratio plot (f clk = 150mhz, f center = 31.9885mhz) max5883 toc08 f out (mhz) output power (dbm) 36 34 32 30 28 -90 -80 -70 -60 -50 -40 -30 -20 f t1 f t2 f t3 f t4 -10 0 -100 26 38 a out = -12db fs bw = 12mhz f t1 = 29.9744mhz f t2 = 30.9998mhz f t3 = 32.9773mhz f t4 = 33.8196mhz 2-tone imd vs. output frequency (1mhz carrier spacing, f clk = 200mhz) max5883 toc07 f out (mhz) 2-tone imd (dbc) 70 60 50 40 30 20 10 -50 -60 -70 -80 -90 -100 -40 080 -12db fs -6db fs sfdr vs. output frequency (f clk = 200mhz, a out = -6db fs) max5883 toc09 f out (mhz) sfdr (dbc) 90 80 70 60 50 40 30 20 10 20 40 60 80 100 0 0 100 i out = 5ma i out = 20ma i out = 10ma
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs 6 _______________________________________________________________________________________ typical operating characteristics (continued) (av dd = dv dd = vclk = 3.3v, external reference, v refio = 1.25v, r l = 50 ? , i out = 20ma, t a = +25 c, unless otherwise noted.) sfdr vs. f out and temperature (f clk = 200mhz, a out = -6db fs, i fs = 20ma) max5883 toc10 f out (mhz) sfdr (dbc) 90 80 60 70 20 30 40 50 10 10 20 30 40 50 60 70 80 90 100 0 0 100 t a = +25 c t a = +85 c t a = -40 c integral nonlinearity vs. digital input code max5883 toc11 digital input code inl (lsb) 4000 3500 3000 2500 2000 1500 1000 500 -0.2 -0.1 0 0.1 0.2 0.3 -0.3 0 4500 differential nonlinearity vs. digital input code max5883 toc12 digital input code dnl (lsb) 4000 3500 3000 2500 2000 1500 1000 500 -0.10 -0.05 0 0.05 0.10 0.15 -0.15 0 4500 power dissipation vs. clock frequency (f out = 10mhz, a out = 0db fs, i out = 20ma) max5883 toc13 f clk (mhz) power dissipation (mw) 175 150 50 75 100 125 110 120 130 140 150 160 170 180 100 25 200 power dissipation vs. supply voltage (f clk = 100mhz, f out = 10mhz, i fs = 20ma) max5883 toc14 supply voltage (v) power dissipation (mw) 3.410 3.355 3.300 3.245 3.190 128 136 144 152 160 120 3.135 3.465 external reference internal reference
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs _______________________________________________________________________________________ 7 pin description pin name function 1, 2, 16, 25 29, 47, 48 n.c. no connection. do not connect to these pins. do not tie these pins together. 3xor xor input pin. xor = 1 inverts the digital input data. xor = 0 leaves the digital input data unchanged. xor has an internal pulldown resistor and may be left unconnected if not used. 4, 9 vclk clock supply voltage. accepts a supply voltage range of 3.135v to 3.465v. bypass each pin with a 0.1f capacitor to the nearest clkgnd. 5, 8 clkgnd clock ground 6 clkp converter clock input. positive input terminal for the converter clock. 7 clkn complementary converter clock input. negative input terminal for the converter clock. 10 pd power-down input. pd pulled high enables the dac s power-down mode. pd pulled low allows for normal operation of the dac. 11, 21, 23 av dd analog supply voltage. accepts a supply voltage range of 3.135v to 3.465v. bypass each pin with a 0.1f capacitor to the nearest agnd. 12, 17, 20, 22, 24, ep agnd analog ground. exposed paddle (ep) must be connected to agnd. 13 refio reference i/o. output of the internal 1.2v precision bandgap reference. bypass with a 0.1f capacitor to agnd. can be driven with an external reference source. 14 fsadj full-scale adjust input. this input sets the full-scale output current of the dac. for 20ma full-scale output current, connect a 2k ? resistor between fsadj and dacref. 15 dacref return path for the current set resistor. for 20ma full-scale output current, connect a 2k ? resistor between fsadj and dacref. 18 ioutn complementary dac output. negative terminal for differential current output. the full-scale output current range can be set from 2ma to 20ma. 19 ioutp dac output. positive terminal for differential current output. the full-scale output current range can be set from 2ma to 20ma. 30 sel0 mode select input sel0. this pin has an internal pulldown resistor; it can be left open to disable the segment-shuffling function (see the segment shuffling section). 31, 43 dv dd digital supply voltage. accepts a supply voltage range of 3.135v to 3.465v. bypass each pin with a 0.1f capacitor to the nearest dgnd. 32, 42 dgnd digital ground 33 b11 data bit 11 (msb) 34 b10 data bit 10 35 b9 data bit 9 36 b8 data bit 8 37 b7 data bit 7
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs 8 _______________________________________________________________________________________ pin name function 38 b6 data bit 6 39 b5 data bit 5 40 b4 data bit 4 41 b3 data bit 3 44 b2 data bit 2 45 b1 data bit 1 46 b0 data bit 0 (lsb) pin description (continued) 1.2v reference current-steering dac function selection block agnd sel0 dgnd dv dd refio fsadj clkn clkp pd av dd ioutp ioutn segment shuffling/latch decoder cmos receiver/input latch 12 digital inputs b0 through b11 max5883 figure 1. simplified max5883 block diagram
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs _______________________________________________________________________________________ 9 detailed description architecture the max5883 is a high-performance, 12-bit, current- steering dac (figure 1) capable of operating with clock speeds up to 200mhz. the converter consists of separate input and dac registers, followed by a cur- rent-steering circuit. this circuit is capable of generat- ing differential full-scale currents in the range of 2ma to 20ma. an internal current-switching network in combi- nation with external 50 ? termination resistors convert the differential output currents into a differential output voltage with a peak-to-peak output voltage range of 0.1v to 1v. an integrated 1.2v bandgap reference, control amplifier, and user-selectable external resistor determine the data converter s full-scale output range. reference architecture and operation the max5883 supports operation with the on-chip 1.2v bandgap reference or an external reference voltage source. refio serves as the input for an external, low- impedance reference source, and as the output if the dac is operating with the internal reference. for stable operation with the internal reference, refio should be decoupled to agnd with a 0.1f capacitor. due to its limited output drive capability, refio must be buffered with an external amplifier, if heavier loading is required. the max5883 s reference circuit (figure 2) employs a control amplifier, designed to regulate the full-scale current i out for the differential current outputs of the dac. configured as a voltage-to-current amplifier, the output current can be calculated as follows: i out = 32 ? i refio - 1 lsb i out = 32 ? i refio - (i out / 2 12 ) where i refio is the reference output current (i refio = v refio /r set ) and i out is the full-scale output current of the dac. located between fsadj and dacref, r set is the reference resistor, which determines the amplifier s output current for the dac. see table 1 for a matrix of different i out and r set selections. analog outputs (ioutp, ioutn) the max5883 outputs two complementary currents (ioutp, ioutn) that can be operated in a single- ended or differential configuration. a load resistor can convert these two output currents into complementary single-ended output voltages. the differential voltage existing between ioutp and ioutn can also be con- verted to a single-ended voltage using a transformer or a differential amplifier configuration. if no transformer is used, the output should have a 50 ? termination to the analog ground and a 50 ? resistor between the outputs. 0.1 f 1.2v reference 10k ? i ref r set dacref fsadj refio i ref = v refio /r set current-steering dac av dd ioutp ioutn figure 2. reference architecture, internal reference configuration r set (k ? ) full-scale current i out (ma) reference current i ref (a) calculated 1% eia std output voltage v ioutp/n * (mv p-p ) 2 62.5 19.2 19.1 100 5 156.26 7.68 7.5 250 10 312.5 3.84 3.83 500 15 468.75 2.56 2.55 750 20 625 1.92 1.91 1000 table 1. i out and r set selection matrix based on a typical 1.200v reference voltage * terminated into a 50 ? load.
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs 10 ______________________________________________________________________________________ although not recommended because of additional noise pickup from the ground plane, for single-ended operation ioutp should be selected as the output, with ioutn connected to agnd. note that a single-ended output configuration has a higher 2nd-order harmonic distortion at high output frequencies than a differential output configuration. figure 3 displays a simplified diagram of the max5883 s internal output structure. clock inputs (clkp, clkn) the max5883 features a flexible differential clock input (clkp, clkn) operating from separate supplies (vclk, clkgnd) to achieve the best possible jitter performance. the two clock inputs can be driven from a single-ended or a differential clock source. for single- ended operation, clkp should be driven by a logic source, while clkn should be bypassed to agnd with a 0.1f capacitor. the clkp and clkn pins are internally biased to vclk/2. this allows the user to ac-couple clock sources directly to the device without external resistors to define the dc level. the input resistance of clkp and clkn is >5k ? . see figure 4 for a convenient and quick way to apply a differential signal created from a single-ended source (e.g., hp 8662a signal generator) and a wideband transformer. these inputs can also be driven from a cmos-compatible clock source; however, it is recom- mended to use sinewave or ac-coupled ecl drive for best performance. data timing relationship figure 5 shows the timing relationship between differ- ential, digital cmos data, clock, and output signals. the max5883 features a 1.25ns hold, a 0.4ns setup, and a 1.8ns propagation delay time. there is a 3.5 clock-cycle latency between clkp/clkn transitioning high/low and ioutp/ioutn. cmos-compatible digital inputs (b0?11) the max5883 features single-ended, cmos-compatible receivers on the bus input interface. these cmos inputs (b0 b11) allow for a voltage swing of 3.3v. segment shuffling (sel0) segment shuffling can improve the sfdr of the max5883 at higher output frequencies and amplitudes. note that an improvement in sfdr can only be achieved at the cost of a slight increase in the dac s noise floor. pin sel0 controls the segment-shuffling function. if sel0 is pulled low, the segment-shuffling function of the dac is disabled. sel0 can also be left open, because an internal pulldown resistor helps to deacti- vate the segment-shuffling feature. to activate the max5883 segment-shuffling function, sel0 must be pulled high. xor function (xor) the max5883 is equipped with a single-ended, cmos- compatible xor input, which may be left open (xor provides an internal pulldown resistor) or pulled down to dgnd, if not used. input data is xored with the bit applied to the xor pin. pulling xor high inverts the input data. pulling xor low leaves the input data nonin- verted. by applying a pseudorandom bit stream to xor and applying inverted data when xor is high, the bit transitions of the digital input data can be decorrelated from the dac output. this allows the user to trou- bleshoot possible spurious or harmonic distortion degradation due to digital feedthrough on the pc board. single-ended clock source (e.g., hp 8662a) 1:1 wideband rf transformer performs single-ended to differential conversion. to dac clkp 0.1 f 0.1 f clkn clkgnd 25 ? 25 ? figure 4. differential clock signal generation i out i out ioutn ioutp current sources current switches av dd figure 3. simplified analog output structure
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs ______________________________________________________________________________________ 11 power-down operation (pd) the max5883 also features an active-high power-down mode, which allows the user to cut the dac s current consumption. a single pin (pd) is used to control the power-down mode (pd = 1) or reactivate the dac (pd = 0) after power-down. enabling the power-down mode of this 12-bit cmos dac allows the overall power consumption to be reduced to less than 1mw. the max5883 requires 10ms to wake up from power-down and enter a fully operational state. applications information differential coupling using a wideband rf transformer the differential voltage existing between ioutp and ioutn can also be converted to a single-ended volt- age using a transformer (figure 6) or a differential amplifier configuration. using a differential transformer- coupled output, in which the output power is limited to 0dbm, can optimize the dynamic performance. however, make sure to pay close attention to the trans- former core saturation characteristics when selecting a transformer for the max5883. transformer core satura- tion can introduce strong 2nd-harmonic distortion, especially at low output frequencies and high signal amplitudes. it is also recommended to center tap the transformer to ground. if no transformer is used, each dac output should be terminated to ground with a 50 ? resistor. additionally, a 100 ? resistor should be placed between the outputs. if a single-ended unipolar output is desirable, ioutp should be selected as the output, with ioutn ground- ed. however, driving the max5883 single ended is not recommended since additional noise is added (from the ground plane) in such configurations. the distortion performance of the dac depends on the load impedance. the max5883 is optimized for a 50 ? double termination. it can be used with a transformer output as shown in figure 7 or just one 50 ? resistor from each output to ground and one 50 ? resistor between the outputs. this produces a full-scale output power of up to 0dbm, depending on the output current setting. higher termination impedance can be used at the cost of degraded distortion performance and increased output noise voltage. adjacent channel leakage power ratio (aclr) testing for cdma- and w-cdma-based base station transceiver systems (bts) the transmitter sections of bts applications serving cdma and w-cdma architectures must generate carri- ers with minimal coupling of carrier energy into the adja- cent channels. a transmit mask (tx mask) exists for this application. the spread-spectrum modulation function applied to the carrier frequency generates a spectral response, which is uniform over a given bandwidth (up to 4mhz) for a w-cdma-modulated carrier. b0 to b15 clkn clkp iout n digital data is latched on the rising edge of clkp output data is updated on the falling edge of clkp n + 1 n + 2 n - 5 n - 3 n - 1 n - 2 n - 4 t setup t hold t pd t ch t cl n - 1 figure 5. detailed timing relationship
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs 12 ______________________________________________________________________________________ * note that due to their own im effects and noise limitations, spectrum analyzers introduce aclr errors, which can falsify the me asure- ment. for a single-carrier aclr measurement greater than 70db, these measurement limitations are significant, becoming even mor e restricting for multicarrier measurement. before attempting an aclr measurement, it is recommended consulting application notes pro- vided by major spectrum analyzer manufacturers that provide useful tips on how to use their instruments for such tests. a dominant specification is aclr, a parameter which reflects the ratio of the power in the desired carrier band to the power in an adjacent carrier band. the specification covers the first two adjacent bands, and is measured on both sides of the desired carrier. according to the transmit mask for cdma and w- cdma architectures, the power ratio of the integrated carrier channel energy to the integrated adjacent chan- nel energy must be >45db for the first adjacent carrier slot (aclr 1) and >50db for the second adjacent carri- er slot (aclr 2). this specification applies to the output of the entire transmitter signal chain. the requirement for only the dac block of the transmitter must be tighter, with a typical margin of >15db, requiring the dac s aclr 1 to be better than 60db. adjacent channel leakage is caused by a single spread- spectrum carrier, which generates intermodulation (im) products between the frequency components located within the carrier band. the energy at one end of the carrier band generates im products with the energy from the opposite end of the carrier band. for single- carrier w-cdma modulation, these imd products are spread 3.84mhz over the adjacent sideband. four con- tiguous w-cdma carriers spread their im products over a bandwidth of 20mhz on either side of the 20mhz total carrier bandwidth. in this four-carrier scenario, only the energy in the first adjacent 3.84mhz sideband is con- sidered for aclr 1. to measure aclr, drive the con- verter with a w-cdma pattern. make sure that the signal is backed off by the peak-to-average ratio, such that the dac is not clipping the signal. aclr can then be measured with the aclr measurement function built into your spectrum analyzer. figure 8 shows the aclr performance for a single w-cdma carrier (f clk = 184.32mhz, f out = 30.72mhz) applied to the max5883 (including measurement system limitations*). figure 9 illustrates the aclr test results for the max5883 with a four-carrier w-cdma signal at an out- put frequency of 30.72mhz and a sampling frequency of 184.32mhz. considerable care must be taken to ensure accurate measurement of this parameter. grounding, bypassing, and power-supply considerations grounding and power-supply decoupling can strongly influence the performance of the max5883. unwanted digital crosstalk may couple through the input, refer- ence, power supply, and ground connections, affecting dynamic performance. proper grounding and power- max5883 t2, 1:1 t1, 1:1 v out , single ended wideband rf transformer t2 performs the differential to single-ended conversion. 50 ? 100 ? 50 ? ioutp ioutn b0?11 12 av dd dv dd vclk agnd dgnd clkgnd figure 6. differential to single-ended conversion using a wideband rf transformer max5883 50 ? 100 ? 50 ? ioutp ioutn b0 b11 12 av dd dv dd vclk agnd dgnd clkgnd outp outn figure 7. max5883 differential output configuration
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs ______________________________________________________________________________________ 13 supply decoupling guidelines for high-speed, high-fre- quency applications should be closely followed. this reduces emi and internal crosstalk that can significant- ly affect the dynamic performance of the max5883. use of a multilayer printed circuit (pc) board with sepa- rate ground and power-supply planes is recommend- ed. high-speed signals should run on lines directly above the ground plane. since the max5883 has sepa- rate analog and digital ground buses (agnd, clkgnd, and dgnd, respectively), the pc board should also have separate analog and digital ground sections with only one point connecting the two planes. digital signals should be run above the digital ground plane and analog/clock signals above the analog/clock ground plane. digital signals should be kept as far away from sensitive analog inputs, reference input sense lines, common-mode input, and clock inputs as practical. a symmetric design of clock input and ana- log output lines is recommended to minimize 2nd-order harmonic distortion components and optimize the dac s dynamic performance. digital signal paths should be kept short and run lengths matched to avoid propagation delay and data skew mismatches. the max5883 supports three separate power-supply inputs for analog (av dd ), digital (dv dd ), and clock (vclk) circuitry. each av dd , dv dd , and vclk input should at least be decoupled with a separate 0.1f capacitor as close to the pin as possible and their opposite ends with the shortest possible connection to the corresponding ground plane (figure 10). all three power-supply voltages should also be decoupled at the point they enter the pc board with tantalum or elec- trolytic capacitors. ferrite beads with additional decou- pling capacitors forming a pi network could also improve performance. the analog and digital power-supply inputs av dd , vclk, and dv dd of the max5883 allow a supply volt- age range of 3.3v 5%. the max5883 is packaged in a 48-pin qfn-ep (package code: g4877-1), providing greater design flexibility, increased thermal efficiency**, and optimized ac performance of the dac. the exposed pad (ep) enables the user to implement grounding techniques, which are necessary to ensure highest performance operation. the ep must be soldered down to agnd. in this package, the data converter die is attached to an ep lead frame with the back of this frame exposed at the package bottom surface, facing the pc board side of the package. this allows a solid attachment of the package to the pc board with standard infrared (ir) flow soldering techniques. a specially created land pat- tern on the pc board, matching the size of the ep (5mm ? 5mm), ensures the proper attachment and grounding of the dac. designing vias*** into the land area and implementing large ground planes in the pc board design allow for highest performance operation of the dac. an array of at least 3 ? 3 vias ( 0.3mm diameter per via hole and 1.2mm pitch between via holes) is rec- ommended for this 48-pin qfn-ep package. 3.5mhz/div analog output power (dbm) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -120 f clk = 184.32mhz f center = 30.72mhz aclr = 71db figure 8. aclr for w-cdma modulation, single carrier 4mhz/div analog output power (dbm) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -120 f clk = 184.32mhz f center = 30.72mhz aclr = 67db figure 9. aclr for w-cdma modulation, four carriers ** thermal efficiency is not the key factor, since the max5883 features low-power operation. the exposed pad is the key element to ensure a solid ground connection between the dac and the pc board s analog ground layer. *** vias connect the land pattern to internal or external copper planes. it is important to connect as many vias as possible to the analog ground plane to minimize inductance.
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs 14 ______________________________________________________________________________________ static performance parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer func- tion, once offset and gain errors have been nullified. for a dac, the deviations are measured at every individual step. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step height and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. offset error the offset error is the difference between the ideal and the actual offset current. for a dac, the offset point is the average value at the output for the two midscale digital input codes with respect to the full scale of the dac. this error affects all codes by the same amount. gain error a gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. settling time the settling time is the amount of time required from the start of a transition until the dac output settles its new output value to within the converter s specified accuracy. glitch energy a glitch is generated when a dac switches between two codes. the largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011...111 to 100...000. the glitch ener- gy is found by integrating the voltage of the glitch at the midscale transition over time. the glitch energy is usu- ally specified in pv-s. dynamic performance parameter definitions signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital sam- ples, the theoretical maximum snr is the ratio of the full- scale analog output (rms value) to the rms quantization error (residual error). the ideal, theoretical maximum snr can be derived from the dac s resolution (n bits): snr db = 6.02 db ? n + 1.76 db however, noise sources such as thermal noise, refer- ence noise, clock jitter, etc., affect the ideal reading; therefore, snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spec- tral components minus the fundamental, the first four harmonics, and the dc offset. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier fre- quency (maximum signal components) to the rms value of their next-largest distortion component. sfdr is usually measured in dbc and with respect to the car- rier frequency amplitude or in db fs with respect to the dac s full-scale range. depending on its test condition, sfdr is observed within a predefined window or to nyquist. two-/four-tone intermodulation distortion (imd) the two-tone imd is the ratio expressed in dbc (or db fs) of either input tone to the worst 3rd-order (or higher) imd products. note that 2nd-order imd products usually fall at frequencies that can be easily removed by digital filtering; therefore, they are not as critical as 3rd-order imds. the two-tone imd performance of the max5883 was tested with the two individual input tone levels set to at least -6db fs and the four-tone performance was tested at an output frequency of 32mhz and amplitude of -12db fs.
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs ______________________________________________________________________________________ 15 adjacent channel leakage power ratio (aclr) commonly used in combination with w-cdma, aclr reflects the leakage power ratio in db between the measured power within a channel relative to its adja- cent channel. aclr provides a quantifiable method of determining out-of-band spectral energy and its influ- ence on an adjacent channel when a bandwidth-limited rf signal passes through a nonlinear device. chip information transistor count: 10,721 process: cmos ferrite bead av cc 1 f10 f47 f analog power-supply source ferrite bead dv cc 1 f10 f47 f digital power-supply source ferrite bead vclk 1 f10 f47 f clock power-supply source av dd agnd max5883 b0 b11 12 0.1 f dgnd 0.1 f vclk clkgnd 0.1 f outp outn dv dd bypassing?ac level bypassing?oard level figure 10. recommended power-supply decoupling and bypassing circuitry
max5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos inputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 32, 44, 48l qfn.eps h 1 2 21-0092 package outline 32,44,48l qfn, 7x7x0.90 mm u h 2 2 21-0092 package outline, 32,44,48l qfn, 7x7x0.90 mm max5883 package code: g4877-1
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs m axim > p roduc ts > h igh-speed data c onverters max5883 3.3v, 12-bit, 200msps high dynamic performance dac with c mos inputs quickview technical documents ordering info more information all ordering information notes: other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 1. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 2. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 3. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 4. devices: 1-4 of 4 m ax5883 fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max5883egm-d qfn;48 pin;50 mm dwg: 21-0092h (pdf) use pkgcode/variation: g4877-1 * -40c to +85c rohs/lead-free: no materials analysis max5883egm-td qfn;48 pin;50 mm dwg: 21-0092h (pdf) use pkgcode/variation: g4877-1 * -40c to +85c rohs/lead-free: no materials analysis max5883egm+d qfn;48 pin;50 mm dwg: 21-0092h (pdf) use pkgcode/variation: g4877+1 * -40c to +85c rohs/lead-free: lead free materials analysis max5883egm+td qfn;48 pin;50 mm dwg: 21-0092h (pdf) use pkgcode/variation: g4877+1 * -40c to +85c rohs/lead-free: lead free materials analysis didn't find what you need? next day product selection assistance from applications engineers parametric search applications help quickview technical documents ordering info more information des c ription key features a pplic ations /u s es key spec ific ations diagram data sheet a pplic ation n otes des ign guides e ngineering journals reliability reports software/m odels e valuation kits p ric e and a vailability samples buy o nline p ac kage i nformation lead-free i nformation related p roduc ts n otes and c omments e valuation kits doc ument ref.: 1 9 -2 8 2 4 ; rev 1 ; 2 0 0 4 -0 1 -2 0 t his page las t modified: 2 0 0 7 -0 8 -0 7 c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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